1. Field
Exemplary embodiments relate to a semiconductor design technology, and more particularly, to a signal transmission technology in a semiconductor device with a stack structure.
2. Description of the Related Art
In order to highly integrate a semiconductor device, various types of packages have been suggested. In particular, in a chip stack type in which a plurality of semiconductor chips are stacked to constitute one semiconductor device, through-semiconductor chip lines are commonly employed to transfer a signal to the plurality of semiconductor chips. In general, since a semiconductor chip is fabricated using a silicon wafer, the through-semiconductor chip lines are referred to as through-silicon vias (TSVs).
FIG. 1 is a conceptual configuration diagram of a semiconductor device that is configured by stacking a plurality of semiconductor chips.
Referring to FIG. 1, a semiconductor device includes a plurality of semiconductor chips, SLICE0, SLICE1 and SLICE2 that are stacked. For reference, FIG. 1 conceptually shows one of various chip stack ways.
The chips SLICE0 to SLICE2 transfer signals among them through through-silicon vias TSV1, TSV2 and TSV3. Repeaters TX and RX are disposed in the respective semiconductor chips SLICE0 to SLICE2 to buffer signals that are transmitted through the TSV1, TSV2 and TSV3.
Even if signals among the chips SLICE0 to SLICE2 may be transmitted through the TSV1, TSV2 and TSV3, one of issues that make it difficult to stack a large number of semiconductor chips resides in operation delay of the repeaters TX and RX for buffering signals of the respective semiconductor chips SLICE0 to SLICE2. That is to say, when transmitting signals, signals reach the chips SLICE0 to SLICE2 at times different from one another due to the operation delay of the repeaters TX and RX.
For example, when the operation speed of repeaters TX and RX of one stage is 200 ps in four-staged stack structure, a delay difference between a lowermost stacked semiconductor chip (“lowermost chip”) and an uppermost stacked semiconductor chip (“uppermost chip”) may reach 600 ps. Assuming that the frequency of an operating clock provided to the chips is 500 MHz, even with a structure in which a plurality of semiconductor chips are simply stacked, a concern is caused in that the delay of a signal may correspond to a half cycle (half tCK).
In other words, when operating at a high speed the device that has the stack structure with the chips SLICE0 to SLICE2, a concern is caused in that operational stability may not be secured, for example, due to the operation delay caused by the repeaters TX and RX that are disposed among the respective semiconductor chips SLICE0 to SLICE2.